Job Description: Title: ASIC/FPGA Design Verification Engineer with UVM Experience Create UVM simulation plan from design specification. Create or modify UVC, Score Board, Monitor, and test cases. Verify until functional coverage and code coverage meet project threshold. Document results. Required Skills: 5+ years of experience 1-2 years of UVM tool Cadence Xcelium verification tool Education: Must have min Bachelor’s in Engineering (no exception, please do not submit candidates without) #J-18808-Ljbffr
